In the formation of semiconductor chips/wafers, integrated circuit devices, such as transistors are formed at the surfaces of semiconductor substrates in the semiconductor chips/wafers. Interconnect structures are then formed over the integrated circuit devices. Metal or solder bumps are formed on the surfaces of the semiconductor chips/wafers, so that the integrated circuit devices can be accessed.
In the packaging of the semiconductor chips, the semiconductor chips are often bonded with package substrates using flip-chip bonding. Solders are used to join the metal bumps in the semiconductor chips to bond pads in the package substrates. Conventionally, eutectic solder materials containing lead (Pb) and tin (Sn) were used for bonding the metal bumps. For example, a commonly used lead-containing eutectic solder has about 63% tin (Sn) and 37% lead (Pb). This combination gives the solder material a suitable melting point and a low electrical resistivity. Further, the eutectic solders have a good crack-resistance.
Lead is a toxic material and hence lead-free solder bumps are preferred. Solutions to replace lead-containing solders with lead-free solders are thus explored. However, the commonly known lead-free solders, such as SnAg, SnAgCu, and their inter-metallic components, are too brittle and hence suffer from the cracking problem. As a result, the solder joints formed of lead-free solders are often not reliable enough and cannot pass reliability tests, such as thermal cycles.
Solder cracking is typically caused by stress. The coefficient of thermal expansion (CTE) mismatch between materials in the package assemblies is one of the main reasons causing the stress. For example, silicon substrates typically have CTE equal to about 3 ppm/° C., low-k dielectric materials may have CTEs equal to about 20 ppm/° C., while the package substrates may have CTEs equal to about 17 ppm/° C. The significant difference in CTEs results in stress being applied to the structure when a thermal change occurs. The use of copper in the metal bumps further worsens the problem. Since copper is rigid, a high stress may be applied on the solders adjoining the copper bumps and hence the solders are more prone to the cracking. For example, the process window for the reflow, which indicates how many repeated reflows the solders can endure without incurring significant cracks, may be too narrow for mass production of the integrated circuits. Also, the electro-migration resistance of the resulting bonding structure is low.